The present invention relates to a chemical mechanical polishing slurry for surfaces of a semiconductor wafer, and more particularly, to a chemical mechanical polishing slurry and a method for using the slurry to remove and polish copper, barrier materials and dielectric materials layered on semiconductor wafer surfaces.
Semiconductor wafers are used to form integrated circuits. The semiconductor wafer typically includes a substrate, such as silicon, upon which dielectric materials, barrier materials, and metal conductors and interconnects are layered. These different materials have insulating, conductive or semi-conductive properties. Integrated circuits are formed by patterning regions into the substrate and depositing thereon multiple layers of dielectric material, barrier material, and metals.
In order to obtain the correct patterning, excess material used to form the layers on the substrate must be removed. Further, to obtain efficient circuits, it is important to have a flat or planar semiconductor wafer surface. Thus, it is necessary to polish certain surfaces of a semiconductor wafer.
Chemical Mechanical Polishing or Planarization (“CMP”) is a process in which material is removed from a surface of a semiconductor wafer, and the surface is polished (planarized) by coupling a physical process such as abrasion with a chemical process such as oxidation or chelation. In its most rudimentary form, CMP involves applying slurry, a solution of an abrasive and an active chemistry, to a polishing pad that buffs the surface of a semiconductor wafer to achieve the removal, planarization, and polishing process. It is not desirable for the removal or polishing process to be comprised of purely physical or purely chemical action, but rather the synergistic combination of both in order to achieve fast uniform removal. In the fabrication of integrated circuits, the CMP slurry should also be able to preferentially remove films that comprise complex layers of metals and other materials so that highly planar surfaces can be produced for subsequent photolithography, or patterning, etching and thin-film processing.
Recently, copper has been used as the metal interconnect for semiconductor wafers. Typically for copper technology, the layers that are removed and polished consist of a copper layer (about 1-1.5 μm thick) on top of a thin copper seed layer (about 0.05-0.15 μm thick). These copper layers are separated from the dielectric material 9 surface by a layer of barrier material (about 50-300 Å thick). The key to obtaining good uniformity across the wafer surface after polishing is by using a slurry that has the correct removal selectivities for each material. If appropriate material removal selectivity is not maintained, unwanted dishing of copper and/or erosion of the dielectric material may occur.
Dishing occurs when too much copper is removed such that the copper surface is recessed relative to the dielectric surface of the semiconductor wafer. Dishing primarily occurs when the copper and barrier material removal rates are disparate. Oxide erosion occurs when too much dielectric material is removed and channels are formed in the dielectric material on the surface of the semiconductor wafer relative to the surrounding regions. Oxide erosion occurs when the dielectric material removal rate is locally much higher than the copper removal rate. Dishing and oxide erosion are area dependent being wafer pattern and pitch dependent as well.
Typical commercial CMP slurries used to remove overfill material and polish semiconductor wafer surfaces have a barrier material removal rate below 500 Å/min. Further, these slurries have a copper to barrier material removal rate selectivity of greater than 4:1. This disparity in removal rates during the removal and polishing of the barrier material results in significant dishing of copper on the surface of the semiconductor wafer and/or poor removal of the barrier material.
Another problem with conventional CMP slurries is that the removal chemistry of the slurry is compositionally unstable. Further, many of the colloidal abrasives agglomerate after relatively short time frames following addition to the supporting chemistry. Both of these problems lead to significant operational obstacles.
A further problem in commercial CMP slurries is that the abrasive materials in the slurries produce defects in the form of micro scratches. These slurries also have poor planarization efficiency, which is the ability of the slurry to polish high points preferentially over low points on the surface of the wafer. Micro scratches and poor planarization efficiency result in integrated circuits with increased defects and a lower yield.
Still another problem of commercial CMP slurries is that the chemicals that make up the slurries produce a copper surface that has a high corrosion tendency post polish.
An object of this invention, therefore, is a CMP slurry that employs a two-step slurry approach. The slurry used in the first step has a high copper removal rate and a comparatively low barrier material removal rate. The slurry used in the second step has a relatively high barrier material removal rate, comparable removal rate for copper and low removal rate on the dielectric material. By using this two-step slurry approach, the first and second slurries can provide the appropriate selectivity ranges to minimize copper dishing and oxide erosion, thereby providing a viable CMP approach to advanced device manufacturing.
Another object of the invention is for the first and second slurries to have stable removal chemistry.
Yet another object is to use abrasives in the first slurry that achieve high copper removal rates, but minimal barrier material removal rates, and to use abrasives in the second slurry that provide superior removal rates on barrier material and low removal rates for copper, which also minimize micro scratch defects and provide very good planarization efficiency.
It is a further object of this invention to employ active copper cleaning chemistry and corrosion inhibitors in the slurry to minimize copper corrosion post polish, and to eliminate post-polish cleaning steps.
These and other objects and advantages of the invention will be apparent to those skilled in the art upon reading the following detailed description and upon reference to the drawings.